1. Technical Field
The present invention relates to a ferroelectric memory device (a ferroelectric storage device), and in particular to a read circuit of a ferroelectric memory device.
2. Related Art
In order to read ferroelectric random access memory (FeRAM), a method employing a latch-type sense amplifier circuit is widely used (see for example JP-A-2000-187990).
However, in this case, the voltage applied to the plate line is voltage-divided between the ferroelectric capacitor capacitance (Cs) and the bit line capacitance (Cbl). Hence an adequate potential is not applied to ferroelectric capacitors by the bit line capacitance (Cbl). Further, because differences in bit line voltages are amplified by a sense amplifier and read, the more the bit line capacitance (Cbl) increases, the smaller is the bit line voltage, so that the sense margin decreases.
Hence read circuits are being studied which can fix bit lines at virtual ground potentials (see for example JP-A-2002-133857).
However, even when using a circuit according to the above JP-A-2002-133857 or similar, as is explained in detail below, readout margins decline (1) when the ferroelectric capacitor capacitance of memory cells deviates greatly from an initial setting, and (2) when the ratio of the memory ferroelectric capacitor capacitance to a tank capacitance changes prominently.
Further, it is important that (3) the readout margin be improved while improving error judgment. Particularly when reading from ferroelectric memory cells, data “0”, for which the charge amount is inherently small, is rapidly transferred to the bit line, and there are cases in which the potential of data “0” is temporarily reversed to the potential of data “1”. In such a reversed state, if the potential difference between the potentials of data “0” and data “1” is expanded, error judgments tend to occur.